The present invention relates generally to integrated circuit devices with bond pads and trim pads. More particularly, the invention relates to integrated circuit devices having bond pads and trim pads on the surface that are manufactured in wafer form and improved configurations for trim pad protection so as to maintain electrical contact between the trim pads and the outside environment during final testing, yet protect the trim pads from environmental stresses, for example, preventing the trim pads from adhering to the contact bumps after the device is attached to an external substrate such as a circuit board.
A wafer level chip scale package (WLCSP) is a package design that is manufactured in wafer form and has overall dimensions substantially equal to that of the silicon die that is within the package. Bond pads on the die provide foundations for contact bumps which allow the die to connect with the outside world. FIG. 1 shows a diagrammatic side view of a silicon die 100 with a bond pad 102 having under bump metallurgy stack 104 and a contact bump 106 disposed above it. Passivation layers 108 and 110 are deposited over the silicon die 100 and the bond pad 102 and then etched away so that the under bump metallurgy stack 104 may be deposited over the bond pad 102. Electrical testing of the bond pads is performed in wafer form using known wafer probing techniques.
In addition to the contact bumps and the bond pads disposed below them, some types of IC devices may also have other metal pads called "trim pads" on the silicon die surface. FIG. 2 shows a diagrammatic top view of a die surface 200 with bond pads 202 and trim pads 204. These "trim pads" are used to trim the product--by driving known current at a specific voltage, product characteristics can be changed to fine tune the performance of an IC circuit device and ensure conformance to the specifications. The trim pads are generally formed from aluminum and thus they will corrode if left exposed in an ambient environment. Also, if they are left exposed when the singulated die is soldered to a substrate, there is a significant risk that the solder may bridge the gap between the particular bond pad pair, thereby shorting out the die. However, forming a protective layer requires a wafer processing operation after the trimming operation which is inefficient.
One approach is to cover the trim pads with a passivation material prior to placing the contact bumps to avoid corrosion. In this scenario, wafer testing must be done a first time to facilitate trimming, which must occur before the trim pads are insulated by the passivation material, and a second time to test for electrical function after the contact bumps have been placed on the dies. This two-part wafer probing process is inefficient, since the wafer must go to a testing facility for trimming, and subsequently, to a manufacturing facility to cover the trim pads and then back to the tester for the wafer probe before the dies are cut and shipped to customers. During the wafer probe testing, the trim pads are covered by insulation, and trimming is no longer possible. Therefore, IC devices that do not meet specifications are discarded even if their problems could have been solved by trimming. These inefficiencies add to the overall cost of manufacturing these IC devices.
The aforementioned problems all contribute to an increase in production cost or a decrease in production yield. Consequently, there is a need for an improved IC packaging to address the aforementioned problems.